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h) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.
i)
The device shall compare the CRC data received from the host with the results of its own CRC
calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one
command, at the end of the command, the device shall report the first error that occurred (see
6.3.2.5 ).
j) The device shall release -DDMARDY within t IORDYZ after the host has negated -DMACK.
k) The host shall neither negate STOP nor negate HSTROBE until at least t ACK after negating -DMACK.
l) The host shall not assert -IOWR, -CS0, -CS1, DA2, DA1, or DA0 until at least tACK after negating
-DMACK.
Figure 12: Ultra DMA Data-Out Burst Host Termination Timing
Notes: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
6.3.2.5 Ultra DMA CRC Calculation
The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra
DMA burst, and reporting any error that occurs at the end of a command.
1.
2.
Both the host and the device shall have a 16-bit CRC calculation function.
Both the host and the device shall calculate a CRC value for each Ultra DMA burst.
3. The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the
beginning of an Ultra DMA burst before any data is transferred.
4. For each STROBE transition used for data transfer, both the host and the device shall calculate a
new CRC value by applying the CRC polynomial to the current value of their individual CRC functions
and the word being transferred. CRC is not calculated for the return of STROBE to the asserted state
after the Ultra DMA burst termination request has been acknowledged.
5. At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to
the device on D[15:00] with the negation of -DMACK.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
P-120_data_sheet_PA-QxBO_Rev100.doc
Page 29 of 76
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